1. Field of the Invention
The present invention relates generally to digital signal processing circuits, including digital-to-analog converters (DACs), and more specifically, to a DAC having filter stages having a selected configuration determined by characteristics of the signal being processed.
2. Background of the Invention
Oversampling DAC circuits typically use filters to generate the final analog signal from the oversampled digital input(s). Such topologies are used widely in DACs such as delta-sigma modulator based DAC integrated circuits, in which conversion of a digital value to an analog signal is accomplished by interpolating the output of the delta-sigma modulator through a series of filter stages. The filtering action is applied to meet certain noise floor requirements at each stage, so that the final output of the filter provides the specified suppression of noise in the generated analog signal.
Typically, the longer and more complex the filter, the better the noise performance of the DAC, but longer and more complex filters have higher power requirements. Since many DACs are employed in battery-powered devices, such as wireless telephones and personal audio players, balancing of power requirements with system performance is necessary.
Therefore, it would be desirable to provide a digital signal processing circuit that has a series of filter stages, in which power consumption can be balanced with noise performance.